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description the M37736M4BXXXGP is a single-chip microcomputer using the 7700 family core. this single-chip microcomputer has a cpu and a bus interface unit. the cpu is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. this microcomputer also includes a 32 khz oscillation circuit, in addition to the rom, ram, multiple-function timers, serial i/o, a-d converter, and others. in the M37736M4BXXXGP, as the multiplex method of the external bus, either of 2 types can be selected. features l number of basic instructions .................................................. 103 l memory size rom ................................................. 32 kbytes ram ................................................ 2048 bytes l instruction execution time the fastest instruction at 25 mhz frequency ...................... 160 ns l single power supply ...................................................... 5 v 10% l low power dissipation (at 25 mhz frequency) ............................................47.5 mw (typ.) l interrupts ............................................................ 19 types, 7 levels l multiple-function 16-bit timer ................................................. 5 + 3 l serial i/o (uart or clock synchronous) ..................................... 3 l 10-bit a-d converter ............................................ 8-channel inputs l 12-bit watchdog timer l programmable input/output, output (ports p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10)..........................84 l clock generating circuit ........................................ 2 circuits built-in l package .........................................................................100-pin qfp application control devices for general commercial equipment such as office automation, office equipment, and others. control devices for general industrial equipment such as communication equipment, and others. pin configuration (top view) mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 1 preliminary notice: this is not a final specification. some parametric limits are subject to change. 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ? p2 3 /a 19 /a 3 /d 3 ? p2 4 /a 20 /a 4 /d 4 ? p2 5 /a 21 /a 5 /d 5 ? p2 6 /a 22 /a 6 /d 6 ? p2 7 /a 23 /a 7 /d 7 ? p3 0 /r/w/wel ? p3 1 /bhe/weh ? p3 2 /ale ? p3 3 /hlda ? evl0 ? evl1 m37736mhbxxxgp v cc v ss ? e/rde ? x out ? x in ? reset ? bsel ? cnv ss ? byte ? p4 0 /hold ? p4 1 /rdy 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p8 6 /r x d 1 ? p8 5 /clk 1 ? p8 4 /cts 1 /rts 1 ? p8 3 /t x d 0 ? p8 2 /r x d 0 /clks 0 ? p8 1 /clk 0 ? p8 0 /cts 0 /rts 0 /clks 1 ? v cc av cc v ref ? av ss v ss p7 7 /an 7 /x cin ? p7 6 /an 6 /x cout ? p7 5 /an 5 /ad trg ? p7 4 /an 4 ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p7 0 /an 0 ? 75 74 73 72 71 80 79 78 77 76 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ? p9 2 /r x d 2 ? p9 3 /t x d 2 ? p9 4 ? p8 7 /t x d 1 ? p9 0 /cts 2 ? p9 1 /clk 2 ? p9 5 ? p9 6 ? p9 7 ? p0 0 /a 0 /cs 0 ? p0 1 /a 1 /cs 1 ? p0 2 /a 2 /cs 2 ? p0 3 /a 3 /cs 3 ? p0 4 /a 4 /cs 4 ? p0 5 /a 5 /rsmp ? p0 6 /a 6 /a 16 ? p0 7 /a 7 /a 17 ? p1 0 /a 8 /d 8 ? p1 1 /a 9 /d 9 ? p1 2 /a 10 /d 10 ? p1 3 /a 11 /d 11 ? p1 4 /a 12 /d 12 ? p1 5 /a 13 /d 13 ? p1 6 /a 14 /d 14 ? p1 7 /a 15 /d 15 ? p2 0 /a 16 /a 0 /d 0 ? p2 1 /a 17 /a 1 /d 1 ? p2 2 /a 18 /a 2 /d 2 p6 5 /tb0 in ? p6 7 /tb2 in / f sub ? p6 6 /tb1 in ? p6 4 /int 2 ? p6 3 /int 1 ? p6 2 /int 0 ? p6 1 /ta4 in ? p6 0 /ta4 out ? p5 7 /ta3 in ? p5 6 /ta3 out ? p5 5 /ta2 in ? p5 4 /ta2 out ? p5 3 /ta1 in ? p5 2 /ta1 out ? p5 1 /ta0 in ? p5 0 /ta0 out ? p10 7 /ki 3 ? p10 6 /ki 2 ? p10 5 /ki 1 ? p10 4 /ki 0 ? p10 3 ? p10 2 ? p10 1 ? p10 0 ? p4 7 ? p4 6 ? p4 5 ? 26 27 28 29 30 p4 4 ? p4 3 ? p4 2 / f 1 ? outline 100p6s-a
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 2 M37736M4BXXXGP block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? clock input x in clock output x out clock generating circuit timer ta4(16) ram 2048 bytes rom 32 kbytes timer ta3(16) timer ta2(16) timer ta1(16) p8(8) input/output port p8 p7(8) input/output port p7 x cin x cout p6(8) input/output port p6 p5(8) input/output port p5 p4(8) input/output port p4 p3(4) input/output port p3 p2(8) input/output port p2 p1(8) input/output port p1 p0(8) input/output port p0 timer ta0(16) watchdog timer timer tb2(16) timer tb1(16) timer tb0(16) uart2(9) uart1(9) uart0(9) a-d converter(10) instruction register(8) data buffer db h (8) data buffer db l (8) processor status register ps(11) direct page register dpr(16) stack pointer s(16) index register y(16) index register x(16) accumulator b(16) arithmetic logic unit(16) accumulator a(16) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) incrementer(24) program address register pa(24) data address register da(24) instruction queue buffer q 2 (8) program counter pc(16) incrementer/decrementer(24) program bank register pg(8) data bank register dt((8) input buffer register ib(16) address bus data bus(even) data bus(odd) x cin x cout enable output e reset input reset (0v) v ss (0v) av ss cnv ss av cc reference voltage input v ref bus method selection input bsel external data bus width selection input byte v cc ? ? ? ? ? ? ? ? ? p9(8) output port p9 ? ? ? ? ? ? ? ? ? p10(8) input/output port p10
3 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. functions of M37736M4BXXXGP memory size input/output ports multi-function timers interrupts clock generating circuit input/output characteristic memory expansion parameter functions number of basic instructions 103 instruction execution time 160 ns (the fastest instruction at external clock 25 mhz frequency) rom 32 kbytes ram 2048 bytes p0 C p2, p4 C p8, p10 8-bit 5 9 p3 4-bit 5 1 output port p9 8-bit 5 1 ta0, ta1, ta2, ta3, ta4 16-bit 5 5 tb0, tb1, tb2 16-bit 5 3 serial i/o (uart or clock synchronous serial i/o) 5 3 a-d converter 10-bit 5 1 (8 channels) watchdog timer 12-bit 5 1 3 external types, 16 internal types each interrupt can be set to the priority level (0 C 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) supply voltage 5 v 10% power dissipation 47.5 mw (at external clock 25 mhz frequency) input/output voltage 5 v output current 5 ma external bus mode a; maximum 16 mbytes, external bus mode b; maximum 1 mbytes operating temperature range C20 to 85 c device structure cmos high-performance silicon gate process package 100-pin plastic molded qfp (100p6s-a)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 4 pin name input/output functions vcc, power source apply 5 v 10% to vcc and 0 v to vss. vss cnvss cnvss input input this pin controls the processor mode. connect to vss for the single-chip mode and the memory expansion mode, and to vcc for the microprocessor mode. _____ reset reset input input when l level is applied to this pin, the microcomputer enters the reset state. these are pins of main-clock generating circuit. connect a ceramic resonator or a quartz- crystal oscillator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. _ e enable output output this pin functions as the enable signal output pin which indicates the access status in the internal bus. in the external bus mode b and the memory expansion mode or the microprocessor mode, ___ this pin output signal rde . byte external data input in the memory expansion mode or the microprocessor mode, this pin determines whether the bus width external data bus has an 8-bit width or a 16-bit width. the data bus has a 16-bit width when l selection input signal is input and an 8-bit width when h signal is input. bsel input in the memory expansion mode or the microprocessor mode, this pin determines the external bus mode. the bus mode becomes the external bus mode a when h signal is input, and the external bus mode b when l signal is input. avcc, analog power power source input pin for the a-d converter. externally connect avcc to vcc and avss to vss. avss source input v ref reference input this is reference voltage input pin for the a-d converter. voltage input p0 0 C p0 7 i/o port p0 i/o in the single-chip mode, port p0 becomes an 8-bit i/o port. an i/o direction register is available so that each pin can be programmed for input or output. these ports are in the input mode when reset. in the memory expansion mode or the microprocessor mode, these pins output address (a 0 C a 7 ) ___ ___ ____ at the external bus mode a, and these pins output signals cs 0 C cs 4 and rsmp, and addresses (a 16 , a 17 ) at the external bus mode b. p1 0 C p1 7 i/o port p1 i/o in the single-chip mode, these pins have the same functions as port p0. when the byte pin is set to l in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (d 8 C d 15 ) is input/output or an address (a 8 C a 15 ) is output. when the byte pin is h and an external data bus has an 8-bit width, only address (a 8 C a 15 ) is output. p2 0 C p2 7 i/o port p2 i/o in the single-chip mode, these pins have the same functions as port p0. in the memory expansion mode or the microprocessor mode, low-order data (d 0 C d 7 ) is input/output or an address is output. when using the external bus mode a, the address is a 16 C a 23 . when using the external bus mode b, the address is a 0 C a 7 . p3 0 C p3 3 i/o port p3 i/o in the single-chip mode, these pins have the same function as port p0. in the memory expansion __ ___ ____ mode or the microprocessor mode, r/ w , bhe , ale, and hlda signals are output at the external ___ ___ ____ bus mode a, and wel , weh , ale, and hlda signals are output at the external bus mode b. p4 0 C p4 7 i/o port p4 i/o in the single-chip mode, these pins have the same functions as port p0. in the memory expansion ____ ___ mode or the microprocessor mode, p4 0 , p4 1 and p4 2 become hold and rdy input pins, and a clock f 1 output pin, respectively. functions of the other pins are the same as in the single-chip mode. however, in the memory expansion mode, p4 2 can be selected as an i/o port. p5 0 C p5 7 i/o port p5 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timers a0 to a3. p6 0 C p6 7 i/o port p6 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins also ___ ___ function as i/o pins for timer a4, input pins for external interrupt input ( int 0 C int 2 ) and input pins for timers b0 to b2. p6 7 also functions as sub-clock f sub output pin. p7 0 C p7 7 i/o port p7 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins function as input pins for a-d converter. additionally, p7 6 and p7 7 have the function as the output pin (x cout ) and the input pin (x cin ) of the sub-clock (32 khz) oscillation circuit, respectively. when p7 6 and p7 7 are used as the x cout and x cin pins, connect a resonator or an oscillator between the both. p8 0 C p8 7 i/o port p8 i/o in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for uart 0 and uart 1. p9 0 C p9 7 output port p9 output port p9 is an 8-bit i/o port. these ports are floating when reset. when writting to the port latch, these ports become the output mode. p9 0 C p9 3 also function as i/o port for uart 2. p10 0 C p10 7 i/o port p10 i/o in addition to having the same functions as port p0 in the single-chip mode, p10 4 C p10 7 also __ __ function as input pins for key input interrupt input ( ki 0 C ki 3 ). output these pins should be left open. pin description x in clock input input bus method select input x out clock output output evl0, evl1 CC
5 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. a-d/uart2 trans./rece. timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 0 watchdog timer dbc brk instruction zero divide reset internal peripheral devices control registers refer to fig. 2 for detail information interrupt vector table 000000 16 00ffff 16 010000 16 01ffff 16 bank 0 16 bank 1 16 fe0000 16 feffff 16 ff0000 16 ffffff 16 bank ff 16 bank fe 16 00ffff 16 008000 16 000000 16 00007f 16 000080 16 internal ram 2048 bytes internal rom 32 kbytes 00fffe 16 00ffd6 16 00007f 16 000000 16 uart1 transmission uart1 receive uart0 transmission uart0 receive ??????????????????? int 1 00087f 16 00ffd6 16 notes 1. internal rom area can be modified. (refer to the section on rom area modification function.) 2. banks 10 16 ?ff 16 cannot be accessed in the external bus mode b. basic function blocks the M37736M4BXXXGP has the same fuanctions as the m37736mhbxxxgp except for the memory allocation and the rom area modification function. refer to the section on the m37736mhbxxxgp. memory the memory map is shown in figure 1. the address space has a capacity of 16 mbytes and is allocated to addresses from 0 16 to ffffff 16 . the address space is divided by 64-kbyte unit called bank. the banks are numbered from 0 16 to ff 16 . however, banks 10 16 C ff 16 cannot be accessed in the external bus mode b. built-in rom, ram and control registers for internal peripheral devices are assigned to bank 0 16 . the 32-kbyte area from addresses 8000 16 to ffff 16 is the built-in rom. addresses ffd6 16 to ffff 16 are the reset and interrupt vector addresses and contain the interrupt vectors. refer to the section on interrupts for details. the 2048-byte area allocated to addresses from 80 16 to 87f 16 is the built-in ram. in addition to storing data, the ram is used as stack during a subroutine call or interrupts. peripheral devices such as i/o ports, a-d converter, serial i/o, timer, and interrupt control registers are allocated to addresses from 0 16 to 7f 16 . additionally, the internal rom area can be modified by software. refer to the section on rom area modification function for details. a 256-byte direct page area can be allocated anywhere in bank 0 16 by using the direct page register (dpr). in the direct page addressing mode, the memory in the direct page area can be accessed with two words. hence program steps can be reduced. fig. 1 memory map
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 6 fig. 2 location of internal peripheral devices and interrupt control registers 00002a uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 /key input interrupt control register port p1 direction register uart 0 transmit/receive mode register uart 0 baud rate register (brg0) uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 baud rate register (brg1) uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 register a-d register 0 a-d register 2 port p1 register port p0 direction register port p2 register port p3 register port p4 register port p5 register port p6 register port p7 register port p8 register a-d control register 0 a-d control register 1 a-d register 1 a-d register 3 a-d register 4 a-d register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start flag one-shot start flag up-down flag timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency selection flag a-d/uart 2 trans./rece. interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register processor mode register 1 oscillation circuit control register 1 serial transmit control register port function control register oscillation circuit control register 0 timer a3 mode register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register reserved area (note) reserved area (note) a-d register 6 a-d register 7 uart 2 transmit/receive control register 1 uart 2 transmit/receive control register 0 uart 2 transmission buffer register uart 2 baud rate register (brg2) uart 2 transmit/receive mode register memory allocation control register reserved area (note) uart 2 receive buffer register note. do not write to this address. port p9 register port p10 register port p10 direction register
7 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. rom area modification function the internal rom size and its address area of the M37736M4BXXXGP can be modified by the memory allocation control registers bit 0 shown in figure 3. figure 5 shows the memory allocation in which the internal rom size and its address area are modified. make sure to write data in the memory allocation control register as the flow shown in figure 4. this rom area modification function is valid in memory expansion mode and single-chip mode. table 1 shows the relationship between memory allocation selection ___ ___ bits and address corresponding to chip-select signals cs 0 and cs 1 in the external bus mode b. when ordering a mask rom, mitsubishi electric corp. produces the mask rom using the data within 32 kbytes (addresses 008000 16 C 00ffff 16 ). it is regardless of the selected rom size (refer to mask rom order confirmation form.) therefore, program ff 16 to the addresses out of the selected rom area in the eprom which you tender when ordering a mask rom. address 00ffff 16 of this microcomputer corresponds to the lowest address of the eprom which you tender. 76543210 ml 0 memory allocation control register memory allocation selection bit rom size (rom area) 0 : 32 kbytes (addresses 008000 16 ?00ffff 16 ) 1 : 16 kbytes (addresses 00c000 16 ?00ffff 16 ) address 63 16 note. write to the memory allocation control register as the flow shown in figure 4. fig. 4 how to write data in memory allocation control register fig. 3 bit configuration of memory allocation control register writing data ?5 16 ?(ldm instruction) writing data ?0 16 ?or ?1 16 ?(ldm instruction) ml 0 selection bit next instruction ?how to write in memory allocation control register
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 8 fig. 5 memory allocation (modification of internal rom area by memory allocation selection bit) ___ ___ table 1. relationship between memory allocation selection bits and addresses corresponding to chip-select signals cs 0 and cs 1 in external bus mode b memory allocation select bit ml 0 0 1 internal rom area 008000 16 C 00ffff 16 00c000 16 C 00ffff 16 access address ___ cs 0 000880 16 C 007fff 16 000880 16 C 007fff 16 ___ cs 1 010000 16 C 03ffff 16 008000 16 C 00bfff 16 010000 16 C 03ffff 16 addressing modes the M37736M4BXXXGP has 28 powerful addressing modes. refer to the mitsubishi semiconductors data book single- chip 16-bit microcomputers for the details of each addressing mode. machine instruction list the M37736M4BXXXGP has 103 machine instructions. refer to the mitsubishi semiconductors data book single-chip 16- bit microcomputers for details. data required for mask rom ordering please send the following data for mask orders. (1) M37736M4BXXXGP mask rom order confirmation form (2) 100p6s mark specification form (3) rom data (eprom 3 sets) sfr internal rom 32 kbytes : external memory area note. banks 10 16 to ff 16 cannot be accessed in the external bus mode b. 000000 16 00007f 16 000080 16 00087f 16 008000 16 00ffff 16 010000 16 ffffff 16 internal ram 2048 bytes sfr (ml 0 ) = (0) (ml 0 ) = (1) rom size : 32 kbytes rom size : 16 kbytes internal rom 16 kbytes 000000 16 00007f 16 000080 16 00087f 16 00c000 16 00ffff 16 010000 16 ffffff 16 internal ram 2048 bytes
9 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. symbol parameter conditions ratings unit vcc power source voltage C0.3 to +7 v avcc analog power source voltage C0.3 to +7 v v i _____ input voltage reset , cnvss, byte C0.3 to +12 v input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3, p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7, p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , v ref , x in, bsel output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3, p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, _ p9 0 C p9 7 , p10 0 C p10 7 , x out , e p d power dissipation ta = 25 c 300 mw t opr operating temperature C20 to +85 c t stg storage temperature C40 to +150 c absolute maximum ratings limits min. typ. max. f(x in ) : operating 4.5 5.0 5.5 f(x in ) : stopped, f(x cin ) = 32.768 khz 2.7 5.5 avcc analog power source voltage vcc v vss power source voltage 0v avss analog power source voltage 0 v high-level input voltage p0 0 C p0 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , _____ p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) high-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in single-chip mode) high-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in memory expansion mode and microprocessor mode) low-level input voltage p0 0 C p0 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , _____ p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel, x cin (note 3) low-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in single-chip mode) low-level input voltage p1 0 C p1 7 , p2 0 C p2 7 (in memory expansion mode and microprocessor mode) high-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 high-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 low-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 low-level peak output current p4 4 C p4 7 , p10 0 C p10 3 low-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 i ol(avg) low-level average output current p4 4 C p4 7 , p10 0 C p10 3 15 ma f(x in ) main-clock oscillation frequency (note 4) 25 mhz f(x cin) sub-clock oscillation frequency 32.768 50 khz unit symbol parameter recommended operating conditions (vcc = 5 v 10%, ta = C20 to +85 c, unless otherwise noted) v vcc power source voltage v ih v ih v ih v il v il v il i oh(peak) i oh(avg) i ol(peak) i ol(peak) i ol(avg) notes 1. average output current is the average value of a 100 ms interval. 2. the sum of i ol(peak) for ports p0, p1, p2, p3, p8, and p9 must be 80 ma or less, the sum of i oh(peak) for ports p0, p1, p2, p3, p8, and p9 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, p7, and p10 must be 100 ma or less, and the sum of i oh(peak) for ports p4, p5, p6, p7, and p10 must be 80 ma or less. 3. limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4. the maximum value of f(x in ) = 12.5 mhz when the main clock division selection bit = 1. 0.8 vcc 0.8 vcc 0.5 vcc 0 0 0 vcc vcc vcc 0.2vcc 0.2vcc 0.16vcc C10 C5 10 20 5 v v v v v v ma ma ma ma ma v i v o C0.3 to vcc + 0.3 v C0.3 to vcc + 0.3 v
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 10 limits min. typ. max. high-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7, p9 0 C p9 7 , p10 0 C p10 7 high-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 i oh = C10 ma 3.1 i ch = C400 m a 4.8 i oh = C10 ma 3.4 i oh = C400 m a 4.8 low-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 , p4 0 C p4 3 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 5 , p8 0 C p8 7, p9 0 C p9 7 , p10 4 C p10 7 v ol low-level output voltage p4 4 C p4 7 , p10 0 C p10 3 i ol = 20 ma 2 v low-level output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 3 i ol = 10 ma 1.9 i ol = 2 ma 0.43 i ol = 10 ma 1.6 i ol = 2 ma 0.4 hysteresis ____ ___ hold , rdy , ta0 in C ta4 in , tb0 in C tb2 in , v t+ C v tC ____ ____ _____ ____ ____ ____ int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , 0.4 1 v _ _ __ _ _ clk 1 , clk 2 , ki 0 C ki 3 v t+ C v tC _____ hysteresis reset 0.2 0.5 v v t+ C v tC hysteresis x in 0.1 0.4 v v t+ C v tC hysteresis x cin (when external clock is input) 0.1 0.4 v high-level input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , _____ p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 7 , x in , reset , cnvss, byte, bsel low-level input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p10 0 C p10 3 , _____ x in, reset , cnvss, byte, bsel v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor v ram ram hold voltage when clock is stopped. 2v unit electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol parameter test conditions v v oh high-level output voltage _ e v oh high-level output voltage p3 0 C p3 2 v ol _ low-level output voltage e v ol low-level output voltage p3 0 C p3 2 v oh v ol i il low-level input current p10 4 C p10 7 , p6 2 C p6 4 i il i ih v oh v ol i oh = C400 m a 4.7 v v v i ol = 2 ma 0.45 v v i ol = 10 ma 2v v i = 0 v v i = 5 v m a ma m a m a 5 C5 C1.0 C5 C0.5 C0.25 i oh = C10 ma 3 v
11 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. v cc = 5 v, f(x in ) = 25 mhz (square waveform), f(f 2 ) = 12.5 mhz, f(x cin ) = 32.768 khz, in operating (note 1) v cc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) = stopped, in operating (note 1) v cc = 5v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when a wit instruction is executed (note 2) v cc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, in operating (note 3) v cc = 5 v, f(x in ) : stopped, f(x cin ) : 32.768 khz, when a wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, unless otherwise noted) max. limits typ. unit min. test conditions symbol parameter 9.5 1.3 10 50 5 20 2.6 19 100 10 1 ma ma m a m a m a m a m a power source current i cc in single-chip mode, output pins are open, and other pins are v ss . notes 1. this applies when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the sign al output stop bit = 1. 2. this applies when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3. this applies when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4. this applies when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1. 20 limits min. typ. max. resolution v ref = v cc 10 bits absolute accuracy v ref = v cc 3 lsb r ladder ladder resistance v ref = v cc 10 25 k w t conv conversion time 9.44 m s v ref reference voltage 2 v cc v v ia analog input voltage 0 v ref v symbol parameter test conditions unit aCd converter characteristics (v cc = av cc = 5 v, v ss = av ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note), unless otherwise noted) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 12 limits min. max. t su(dCe) data input setup time (external bus mode a) 32 ns t su(dCrde) data input setup time (external bus mode b) 32 ns t su(rdyC f 1) ___ rdy input setup time 55 ns t su(holdC f 1) ____ hold input setup time 55 ns t h(eCd) data input hold time (external bus mode a) 0 ns t h(rdeCd) data input hold time (external bus mode b) 0 ns t h( f 1Crdy) ___ rdy input hold time 0ns t h( f 1Chold) ____ hold input hold time 0ns limits min. max. t su(p0dCe) port p0 input setup time 60 ns t su(p1dCe) port p1 input setup time 60 ns t su(p2d-e) port p2 input setup time 60 ns t su(p3dCe) port p3 input setup time 60 ns t su(p4dCe) port p4 input setup time 60 ns t su(p5dCe) port p5 input setup time 60 ns t su(p6dCe) port p6 input setup time 60 ns t su(p7dCe) port p7 input setup time 60 ns t su(p8dCe) port p8 input setup time 60 ns t su(p10dCe) port p10 input setup time 60 ns t h(eCp0d) port p0 input hold time 0ns t h(eCp1d) port p1 input hold time 0ns t h(eCp2d) port p2 input hold time 0ns t h(eCp3d) port p3 input hold time 0ns t h(eCp4d) port p4 input hold time 0ns t h(eCp5d) port p5 input hold time 0ns t h(eCp6d) port p6 input hold time 0ns t h(eCp7d) port p7 input hold time 0ns t h(eCp8d) port p8 input hold time 0ns t h(eCp10d) port p10 input hold time 0ns limits min. max. t c external clock input cycle time (note 3) 40 ns t w(h) external clock input high-level pulse width (note 4) 15 ns t w(l) external clock input low-level pulse width (note 4) 15 ns t r external clock rise time 8ns t f external clock fall time 8ns timing requirements (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted (note)) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. input signals rise/fall time must be 100 ns or less, unless otherwise noted. external clock input unit symbol parameter unit symbol parameter single-chip mode notes 3. when the main clock division selection bit = 1, the minimum value of tc = 80 ns. 4. when the main clock division selection bit = 1, values of tw (h) / tc and tw (l) / tc must be set to values from 0.45 through 0.55. unit symbol parameter memory expansion mode and microprocessor mode
13 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. limits min. max. t c(ta) tai in input cycle time 80 ns t w(tah) tai in input high-level pulse width 40 ns t w(tal) tai in input low-level pulse width 40 ns unit symbol parameter timer a input (count input in event counter mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width (note) 160 ns t w(tal) tai in input low-level pulse width (note) 160 ns unit symbol parameter timer a input (gating input in timer mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in one-shot pulse mode) limits min. max. t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in pulse width modulation mode) limits min. max. t c(up) tai out input cycle time 2000 ns t w(uph) tai out input high-level pulse width 1000 ns t w(upl) tai out input low-level pulse width 1000 ns t su(upCt in ) tai out input setup time 400 ns t h(t in Cup) tai out input hold time 400 ns unit symbol parameter timer a input (up-down input in event counter mode) unit symbol parameter timer a input (two-phase pulse input in event counter mode) limits min. max. t c(ta) taj in input cycle time 800 ns t su(taj in Ctaj out ) taj in input setup time 200 ns t su(taj out Ctaj in ) taj out input setup time 200 ns note. limits change depending on f(x in ). refer to data formulas. note. limits change depending on f(x in ). refer to data formulas.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 14 limits min. max. t w(inh) ___ int i input high-level pulse width 250 ns t w(inl) ___ int i input low-level pulse width 250 ns t w(kil) _ _ _ kl i input low-level pulse width 250 ns limits min. max. t c(ck) clk i input cycle time 200 ns t w(ckh) clk i input high-level pulse width 100 ns t w(ckl) clk i input low-level pulse width 100 ns t d(cCq) t x d i output delay time 80 ns t h(cCq) t x d i hold time 0ns t su(dCc) r x d i input setup time 30 ns t h(cCd) r x d i input hold time 90 ns limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns limits min. max. t c(ad) _____ ad trg input cycle time (minimum allowable trigger) 1000 ns t w(adl) _____ ad trg input low-level pulse width 125 ns limits min. max. t c(tb) tbi in input cycle time (one edge count) 80 ns t w(tbh) tbi in input high-level pulse width (one edge count) 40 ns t w(tbl) tbi in input low-level pulse width (one edge count) 40 ns t c(tb) tbi in input cycle time (both edges count) 160 ns t w(tbh) tbi in input high-level pulse width (both edges count) 80 ns t w(tbl) tbi in input low-level pulse width (both edges count) 80 ns unit symbol parameter timer b input (count input in event counter mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse period measurement mode) timer b input (pulse width measurement mode) unit symbol parameter a-d trigger input unit serial i/o unit symbol parameter symbol parameter symbol parameter unit symbol parameter _____ _ _ _ _ external interrupt int i input, key input interrupt ki i input note. limits change depending on f(x in ). refer to data formulas. note. limits change depending on f(x in ). refer to data formulas.
15 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. data formulas timer a input (gating input in timer mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time t w(tah) tai in input high-level pulse width t w ( tal ) tai in input low-level pulse width ns ns ns 8 5 10 9 2 f(f 2 ) timer a input (external trigger input in one-shot pulse mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time ns timer b input (in pulse period measurement mode or pulse width measurement mode) limits min. max. symbol parameter unit ns ns ns t c(tb) tbi in input cycle time t w(tbh) tbi in input high-level pulse width t w(tbl) tbi in input low-level pulse width 8 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 8 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) note. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37736mhbxxxgp.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 16 limits min. max. t d(eCp0q) port p0 data output delay time 80 ns t d(eCp1q) port p1 data output delay time 80 ns t d(eCp2q) port p2 data output delay time 80 ns t d(eCp3q) port p3 data output delay time 80 ns t d(eCp4q) port p4 data output delay time 80 ns t d(eCp5q) port p5 data output delay time 80 ns t d(eCp6q) port p6 data output delay time 80 ns t d(eCp7q) port p7 data output delay time 80 ns t d(eCp8q) port p8 data output delay time 80 ns t d(eCp9q) port p9 data output delay time 80 ns t d(eCp10q) port p10 data output delay time 80 ns unit symbol parameter test conditions switching characteristics (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85c, f(x in ) = 25 mhz (note), unless otherwise noted) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. fig. 6 measuring circuit for ports p0 C p10 and f 1 fig. 6 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 p10 f 1 e 50 pf
17 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. [external bus mode a] memory expansion mode and microprocessor mode (v cc = 5 v 10%, v ss = 0 v, ta = 25 c, f(x in ) = 25 mhz (note 1), unless otherwise noted) symbol parameter t d(eCdq) t h(eCdq) address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time limits wait mode min. max. test conditions unit 45 5 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 12 87 12 87 18 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t d(anCe) t d(aCe) t d(aleCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t w(el) data output delay time data hold delay time _ e pulse width floating start delay time floating release delay time ___ bhe output delay time _ r/ w output delay time ___ bhe hold time _ r/ w hold time no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 fig. 6 (note 2) f 1 output delay time t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1 ) t d( f 1 Chlda) ____ hlda output delay time 0 18 50 notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0.
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 18 [external bus mode a] memory expansion mode and microprocessor mode bus timing data formulas (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (max., note), unless otherwise noted) address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time _ e pulse width floating start delay time floating release delay time no wait wait 1 wait 0 45 5 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) ns ns ns ns ns ns ns ns ns ns no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) ns ns 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 20 C 28 C 33 C 28 C 33 C 22 C 22 unit symbol parameter limits wait mode min. max. t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) no wait wait 1 wait 0 ___ bhe output delay time _ r/ w output delay time t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC f 1) f 1 output delay time _ r/ w hold time ___ bhe hold time 0 18 ns ns ns ns ns ns ns ns notes 1. this applies when the main-clock division selection bit = 0. 2. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37736mhbxxxgp.
19 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. [external bus mode b] memory expansion mode and microprocessor mode (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (note 1), unless otherwise noted) symbol parameter chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold delay time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time f 1 output delay time ____ hlda output delay time limits wait mode min. max. test conditions t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) t d( f 1 Chlda) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 5 18 50 12 87 4 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 48 128 10 0 0 fig. 6 (note 2) no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 20 [external bus mode b] memory expansion mode and microprocessor mode bus timing data formulas (v cc = 5 v 10%, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz (max., note1), unless otherwise noted) 45 5 18 limits wait mode min. max. symbol parameter unit 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) ns ns no wait wait 1 wait 0 t d(csCwe) t d(csCrde) t h(weCcs) t h(rdeCcs) t d(anCwe) t d(anCrde) t d(aCwe) t d(aCrde) t h(weCan) t h(rdeCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCwe) t d(aleCrde) t d(weCdq) t h(weCdq) t w(we) t pxz(rdeCdz) t pzx(rdeCdz) t w(rde) t d(rsmpCwe) t d(rsmpCrde) t h( f 1 Crsmp) t d(weC f 1 ) t d(rdeC f 1 ) ns 4 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 3 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) ns ns ns ns ns ns ns ns ns ns no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) ns ns 1 5 10 9 2 f(f 2 ) 2 5 10 9 2 f(f 2 ) 4 5 10 9 2 f(f 2 ) 1 5 10 9 2 f(f 2 ) ns ns ns ns ns ns 0 0 chip-select output delay time chip-select hold time address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time ___ ___ wel / weh pulse width floating start delay time floating release delay time ___ rde pulse width ____ rsmp output delay time ____ rsmp hold time f 1 output delay time C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 20 C 32 C 32 C 30 C 28 C 33 notes 1. this applies when the main-clock division selection bit = 0. 2. f(f 2 ) represents the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 10 in data sheet m37736mhbxxxgp.
21 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. timing diagram t w(h) t d(e?iq) t d(e?2q) t d(e?3q) t d(e?4q) t d(e?5q) t d(e?6q) t d(e?7q) t d(e?8q) port pi output (i = 0 ?10) port pi input (i = 0 ?8, 10) port p1 output port p1 input port p2 output port p2 input port p3 output port p3 input e x in port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input single-chip mode t su(pid?) t h(e?id) t d(e?1q) t r t f t w(l) t c t su(p1d?) t h(e?1d) t su(p2d?) t h(e?2d) t su(p3d?) t h(e?3d) t su(p4d?) t h(e?4d) t su(p5d?) t h(e?5d) t su(p6d?) t h(e?6d) t su(p7d?) t h(e?7d) t su(p8d?) t h(e?8d)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 22 tai in input tai out input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in ?p) t su(up? in ) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) in event count mode taj in input taj out input t c(ta) t su(taj in ?aj out ) t su(taj in ?aj out ) t su(taj out ?aj in ) t su(taj out ?aj in ) in event counter mode (when two-phase pulse input is selected) t c(tb) t w(tbh) t w(tbl) tbi in input
23 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(knl) t d(c?) t su(d?) t h(c?) t w(inh) ad trg input clk i txd i rxd i inti input kli input t h(c?)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 24 memory expansion mode and microprocessor mode (when wait bit = 1) ( when wait bit = 0) (when wait bit = 1 or 0 in common) test conditions ? v cc = 5 v 10% ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timin g volta g e : v ol = 0.8 v, v oh = 2.0 v f 1 rdy input f 1 e or rde, wel, weh rdy input f 1 hold input hlda output t su(rdyC f 1 ) t h( f 1 Crdy) t su(rdyC f 1 ) t h( f 1 Crdy) t su(holdC f 1 ) t d( f 1 Chlda) t h( f 1 Chold) t d( f 1 Chlda) e or rde, wel, weh
25 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. [external bus mode a] memory expansion mode and microprocessor mode (no wait : when wait bit = 1) f 1 t d(e- f 1) t d(an-e) t w(ale) t d(ale-e) t su(a-ale) t d(a-e) t d(e-dq) t h(ale-a) t d(bhe-e) t h(e-bhe) t d(r/w-e) t h(e-r/w) t h(e-dq) t pxz(e-dz) t su(d-e) t h(e-d) t pzx(e-dz) t h(e-an) t d(e- f 1) t w(el) t w(h) e an ale am/dm dm in bhe r/ w address address address data data address address address t f t r t c t w(l) test conditions v cc = 5 v ?10% output timing voltage : v ol = 0.8 v, v oh = 2.0 v data input dm in : v il = 0.8 v, v ih = 2.5 v x in
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 26 t w(ale) t c address t w(l) t w(h) t f t r address address t d(e f 1 ) t d(an?) t d(ale?) t su(aale) t h(ale?) t d(a?) t d(e?q) t h(e?) t pzx(e?z) t h(e?he) t su(de) test conditions ?vcc = 5 v 10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input dm in : v il = 0.8 v, v ih = 2.5 v data address data t d(e f 1 ) address t pxz(e?z) t w(el) t h(e?n) t h(e?q) t h(e?/w) t d(r/w?) t d(bhe?) x in e an ale am/dm dm in bhe r /w f 1 [external bus mode a] memory expansion mode and microprocessor mode (wait 1 : the external area is accessed when wait bit = 0 and wait selection = 1.)
27 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. [external bus mode a] t h(ale?) t d(ale?) t d(e?q) t w(l) t w(h) t f t c t r memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = ??and wait selection bit = ??) x in f 1 address address address address data an ale am/dm dm in r /w t d(an?) t w(ale) t su(a?le) t h(e?q) t d(a?) t pxz(e?z) t pzx(e?z) t h(e?) t su(d?) address data address test conditions ?vcc = 5 v 10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input dm in : v il = 0.8 v, v ih = 2.5 v t d(e f 1 ) t d(e f 1 ) t d(r/w?) t h(e?/w) t w(el) t h(e?n) t d(bhe?) t h(e?he) e bhe
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 28 [external bus mode b] memory expansion mode and microprocessor mode (no wait : when wait bit = 1) t w(we) t h(weCdq) t w(l) t w(h) t f t r t c x in f 1 cs 0 C cs 4 an ale am/dm t d(csCwe) t d(csCrde) t h(we Ccs) t h(rdeC cs) address t d(anCwe) t d(anCrde ) t h(rde Can) t w(ale) t d(ale Cwe) address address t su(aCale) t h(ale Ca) t d(aCwe) t d(aCrde) t d(ale Crde) t pxz(rde Cdz) t pzx(rdeCdz) address data address address wel, weh t h(weCan) t d(weCdq) dm in rde rsmp test conditions ? vcc = 5 v 10% ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t su(dCrde) t h(rdeCd) t w(rde) t d(rsmpCwe) t h( f 1 Crsmp) t d(rsmpCrde) data t d(rdeC f 1 ) t d(weC f 1 ) t d(weC f 1 ) t d(rdeC f 1 )
29 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. [external bus mode b] memory expansion mode and microprocessor mode (wait 1 : the external area is accessed when wait bit = 0 and wait selection bit = 1.) t c t w(l) t w(h) t f t r t w(ale) t d(anwe) am/dm address t d(cs?de) t w(rde) t d(rde- f 1 ) x in f 1 address address cs 0 ? cs 4 an ale wel, weh dm in rde rsmp t d(we f 1 ) t d(rde f 1 ) t d(cs?e) t d(ale?e) t h(rde?n) t su(a?le) t h(ale?) t d(a?e) t d(we?q) t w(we) t d(a?de) t pzx(rde?z) t h(rde?s) t h(rde?) t su(drde) t d(rsmp?e) t h( f 1 ?smp) t d(rsmp?de) test conditions ?vcc = 5 v 10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input dm in : v il = 0.8 v, v ih = 2.5 v data address t h(we?s) data t d(we f 1 ) t h(we-an) t d(ale?de) t d(an?de) t h(we?q) address t pxz(rde?z)
preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer 30 [external bus mode b] memory expansion mode and microprocessor mode (wait 0 : the external memory area is accessed when wait bit = 0 and wait selection bit = 1.) t c t r t h(ale?) t d(ale?e) t d(we?q) t w(l) t w(h) t f x in f 1 address address address address data cs 0 ? cs 4 an ale am/dm wel , weh dm in rde rsmp t d(cs?e) t h(we?s) t d(cs?de) t d(an?e) t w(ale) t h(we?n) t d(an?de) t h(rde?n) t su(a?le) t h(we?q) t d(ale?de) t d(a?e) t w(we) t d(a?de) t pxz(rde?z) t pzx(rde?z) t h(rde?s) t h(rde?) t su(d?de) t w(rde) t d(rsmp?e) t h( f 1 ?smp) t d(rsmp?de) address data address test conditions ?vcc = 5 v 10% ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input dm in : v il = 0.8 v, v ih = 2.5 v t d(we f 1 ) t d(rde f 1 ) t d(rde f 1 ) t d(we f 1 )
31 mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change. package outline
? 1997 mitsubishi electric corp. h-lf480-a ki-9703 printed in japan (rod) 2 new publication, effective mar. 1997. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originat ing in the use of any product data, diagrams, charts or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. mitsubishi microcomputers M37736M4BXXXGP single-chip 16-bit cmos microcomputer preliminary notice: this is not a final specification. some parametric limits are subject to change.

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